1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods therefor, and more particularly, relates to a semiconductor device including wires consisting of elemental titanium (Ti) or a Ti-containing conductive material and to a manufacturing method therefor.
2. Description of the Related Art
A conventional method for manufacturing a multilayer wiring structure including Ti layers will be described with reference to FIGS. 3A to 3F.
As shown in FIG. 3A, a first interlayer insulating film 200, which is formed of borophosphosilicate glass (BPSG) and provided on a surface of a silicon substrate, is planarized by chemical mechanical polishing (CMP). On the surface of the first interlayer insulating film 200 thus planarized, a second interlayer insulating film 201 of 100 nm thick consisting of silicon oxide is formed by chemical vapor deposition (CVD).
As shown in FIG. 3B, on the second interlayer insulating film 201, a Ti film 202 having a thickness of 40 nm, a titanium nitride (TiN) film 203 having a thickness of 20 nm, and tungsten (W) film 204 having a thickness of 100 nm are deposited in that order. In addition, on the W film 204, an antireflection film 205 formed of SiON is deposited.
As shown in FIG. 3C, a resist pattern 206 is formed on the antireflection film 205. The resist pattern 206 covers areas at which wires are to be formed. Etching from the antireflection film 205 to the Ti film 202 is performed by using the resist pattern 206 as a mask. After etching, the resist pattern 206 is removed.
As shown in FIG. 3D, multilayer wires 207 each consisting of the Ti film 202, the TiN film 203, and the W film 204 are formed.
As shown in FIG. 3E, a third interlayer insulating film 208 of 10 to 20 nm thick consisting of silicon nitride is formed by low pressure CVD so as to cover the exposed surface of the second interlayer insulating film 201 and the multilayer wires 207.
As shown in FIG. 3F, on the third interlayer insulating film 208, a fourth interlayer insulating film 209 of 700 nm thick consisting of silicon oxide is formed by high density plasma CVD. On the fourth interlayer insulating film 209, a fifth interlayer insulating film 210 of 350 nm thick consisting of silicon nitride is formed by plasma enhanced CVD. The bottom of the multilayer wire 207 is in contact with the second interlayer insulating film 201, and the side surfaces and the upper surface of the multilayer wire 207 are in contact with the third interlayer insulating film 208, so that the multilayer wire 207 is insulated from the other conductive regions.
However, when the degree of integration of a semiconductor integrated circuit device is increased, it was found that insulation defects between wires or between a wire and another conductive plug were likely to occur.